伊藤秀男（いとう ひでお）の最近の学会発表など
■■■■論文■■■■
●Masato Kitakami, Bochuan Cai * and Hideo Ito（*大学院学生） : A Checkpointing Method with Small
Checkpoint Latency, IEICE Trans. Inf. & Syst., Vol.E91-D, No.3, pp.857-861, March 2008.
●Yoichi Sasaki, Kazuteru Namba and Hideo Ito, "Circuit and Latch Capable of Masking Soft Errors with
Schmitt Trigger," J. Electronic Test.: Theory & Appl., Vol. 24, No.1-3, pp.11-19, June 2008.
●Kentaroh Katoh, Kazuteru Namba and Hideo Ito : Two-Stage Stuck-at Fault Test Data Compression
Using Scan Flip-Flop with Delay Fault Testability, IPSJ Trans. System LSI Design Methodology, Vol.1,
pp.91-108, Aug. 2008.
●Kazuteru Namba and Hideo Ito : Test Compression for Robust Testable Path Delay Fault Testing Using
Interleaving and Statistical Coding, IEICE Trans. Inf. & Syst., Vol.E92-D, No.2, pp.269-282, Feb., 2009.
●Kentaroh Katoh, Kazuteru Namba and Hideo Ito : Design for Delay Fault Testability of 2-Rail Logic
Circuits, IEICE Trans. Inf. & Syst., Vol.E92-D, No.2, pp.336-341, Feb., 2009.
●Kazuteru Namba, Yoshikazu Matsui and Hideo Ito, "Test Compression for IP Core Testing with
Reconfigurable Network and Fixing-Flipping Coding," J. Electronic Test.: Theory & Appl., Vol. 25, No. 1,
pp.97-105, Feb. 2009.
●Kentaroh Katoh, Kazuteru Namba and Hideo Ito : Design for Delay Fault Testability of Dual Circuits
Using Master and Slave Scan Path, IEICE Trans. Inf. & Syst., Vol.E92-D, No.3, pp.433-442, March., 2009.
●Shuagyu Ruan*, Kazuteru Namba and Hideo Ito（*大学院学生） : Construction of Soft-Error-Tolerant
FF with Wide Error Pulse Detecting Capability, IEICE Trans. Inf. & Syst., Vol.E92-D, No.8, pp.1534-1541,
August, 2009.
●Kazuteru Namba and Hideo Ito : Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits,
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.9,
pp.2295-2303, Sep.., 2009.
●田辺融, 加藤健太郎，難波一輝，伊藤 秀男："差分によるＶＬＳＩ回路の遅延測定"，電子情報通信
学会論文誌Ｄ，Vol.J93-D, No.4, pp.460-468, 2010（平成22年4月).
●Kazuteru Namba, Takashi Ikeda*, and Hideo Ito（*大学院学生）, "Construction of SEU Tolerant Flip-
Flop Allowing Enhanced Scan Delay Fault Testing," IEEE Trans. on Very Large Scale Integration (VLSI)
Systems, Vol. 18, No. 9, pp.1265-1276, Sep. 2010.
●Kazuteru Namba, Kengo, Nakashima*, and Hideo Ito（*大学院学生）, : "Single-Event-Upset Tolerant RS Flip-
Flop with Small Area", IEICE TRANSACTIONS on Information and Systems Vol.E93-D No.12 pp.3407-3409, 2010.
●Kazuteru Namba and Hideo Ito : Chiba Scan Delay Fault Testing with Short Test Application Time, J
Electron Test, Vol26, pp.667-677, 2010.
●Kazuteru Namba, and Hideo Ito, : " Constructiion of BILBO FF with Soft Error Tolerant Capability ", IEICE
TRANSACTIONS on Information and Systems Vol.E94-D No.5 pp.1045-1050, 2011.
■■■■国際会議発表など■■■■
●Kentaroh Katoh, Kazuteru NAMBA, and Hideo Ito : Design for Delay Fault Testing of 2-Rail Logic
Circuits, Proceedings of Indonesia-Japan Joint Scientific Symposium 2008, (Chiba), pp.57-62-,
Sep.10(2008).
●Shuangyou Ruan*, Kazuteru Namba,, and Hideo Ito （*大学院学生）: Soft Error Hardened FF Capable
of Detecting Wide Error Pulse, 23rd IEEE International Symposium on Defect and Fault Tolerance in
VLSI Systems (DFT2008), (Boston), pp.272-280, Oct.2(2008).
●Kazuteru Namba,, and Hideo Ito : Delay Fault Testability on Two-Rail Logic Circuits, 23rd IEEE
International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2008), (Boston), pp.482-
490, Oct.3(2008).
●Kazuteru Namba,, and Hideo Ito :Path Delay Fault Test Set for Two-Rail Logic Circuits, 2008 14th
IEEE Pacific Rim International Symposium on Dependable Computing (PRDC2008), (Taipei), pp.347-
348, Dec.15(2008).
●Takumi Hoshi, Kazuteru Namba,, and Hideo Ito : Testing of Switch Bloacks in Three-Dimensional
FPGA, 2009 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2009),
(Chicago), pp.227-235, Oct.3(2009).
●Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru NAMBA, and Hideo Ito : A Delay
Measurement Technique Using Signature Registers, IEEE Eigteenth Asian Test Symposium (ATS'09),
(Taichung), pp-157-162, Nov. 23-26 (2009).
●Kentaroh Katoh, Kazuteru NAMBA, and Hideo Ito : A Low-Area and Short-Time Scan-Based Embedded
Delay Measurement Using Signature Registers, 2010 IEEE International Symposium on VLSI Design,
Automation and Test (2010 VLSI-DAT), (Hsinchu, Taiwan), pp-311-314, April 26-29 (2010).
●Kazuteru Namba, and Hideo Ito : Soft Error Tolerant BILBO FF, 2019 IEEE International Symposium
on Defect and Fault Tolerance in VLSI Systems (DFT2010), (Kyoto), pp.73-81, Oct.6(2010).
●Kazuteru Namba, Masatoshi Sakata, and Hideo Ito : Single Event Induced Double Node Upset Tolerant
Latch, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2010),
(Kyoto), pp.280-288, Oct.7(2010).
●Kentaroh Katoh, Kazuteru NAMBA, and Hideo Ito : A Low-Area On-Chip Delay Measurement Using
Embedded Delay Measurement Circuit, 2010 19th IEEE Asian Test Symposium (ATS 2010), (Shanghai),
pp-343-348, Dec. 1-4 (2010).
■■■■著書など■■■■
●伊藤秀男，倉田是*（*流通経済大）：入門計算機システム，朝倉書店，2000年3月1日.
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