難波 一輝


現在の研究テーマ

VLSI のテスト容易化設計
遅延故障テスト
高信頼設計(フォールトトレランス)

所属学会

電子情報通信学会
IEEE
情報処理学会


発表論文

原著論文

筆頭

  1. Kazuteru Namba, "Master-slave FF using DICE capable of tolerating soft errors occurring around clock edge, " IEICE Trans. Inf. & Syst., (掲載予定).
  2. Kazuteru Namba and Fabrizio Lombardi, "Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)," IEEE Trans. Comput. Vol.68, No.2, pp.301-306, Feb. 2019.
  3. Kazuteru Namba and Fabrizio Lombardi, "A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits," IEEE Trans. Comput. Vol.67, No.10, pp.1525-1531, Oct. 2018.
  4. Kazuteru Namba and Fabrizio Lombardi, "On coding for endurance enhancement and error control of phase change memories (PCMs) with write latency reduction," IEEE Trans. Very Large Scale Integr. Syst., Vol.26, No.2, pp.230-238, Feb. 2018.
  5. Kazuteru Namba and Fabrizio Lombardi, "Parallel decodable multi-level unequal burst error correcting codes for memories of approximate systems," IEEE Trans. Comput., Vol.65, No.12, pp.3794-3801, Dec. 2016.
  6. Kazuteru Namba and Fabrizio Lombardi, "A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems," IEEE Trans. Multi-Scale Comput. Syst., Vol.2, No.4, pp.291-296, Sep. 2016.
  7. Kazuteru Namba and Fabrizio Lombardi, "Single multiscale-symbol error correction codes for multiscale storage systems," IEEE Trans. Comput., Vol. 65, No. 6, pp.2005-2009, Jun 2016.
  8. Kazuteru Namba and Fabrizio Lombardi, "High-speed parallel decodable non-binary single-error correcting (SEC) codes," IEEE Trans. Device Mater. Reliab., Vol. 16, No. 1, pp.30-37, Mar. 2016.
  9. Kazuteru Namba and Fabrizio Lombardi, "Parallel decodable two-level unequal burst error correcting codes," IEEE Trans. Comput., Vol. 64, No. 10, pp. 2902-2911, Oct. 2015.
  10. Kazuteru Namba and Fabrizio Lombardi, "Non-binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)," IEEE Trans. Comput., Vol. 64, No. 7, pp.2092-2097, Jul. 2015.
  11. Kazuteru Namba and Fabrizio Lombardi, "A single and adjacent symbol error correcting parallel decoder for Reed-Solomon codes," IEEE Trans. Device Mater. Reliab., Vol. 15, No. 1, pp.75-81, Mar. 2015.
  12. Kazuteru Namba, Salvatore Pontarelli, Marco Ottavi and Fabrizio Lombardi, "A single-bit and double-adjacent error correcting parallel decoder for multiple-bit error correcting BCH codes," IEEE Trans. Device Mater. Reliab., Vol.14, No.2, pp.664-671, Jun. 2014.
  13. Kazuteru Namba and Fabrizio Lombardi, "Concurrent Error Detection of Binary and non-Binary OLS Parallel Decoders," IEEE Trans. Device Mater. Reliab. Vol.14, No.1, pp.112-120, Mar. 2014.
  14. Kazuteru Namba, Takashi Katagiri and Hideo Ito, "Timing-error-detecting Dual-edge-triggered Flip-flop," J. Electronic Test.: Theory & Appl., Vol.29, No.4, pp.545-554, Aug. 2013.
  15. Kazuteru Namba, Nobuhide Takashina and Hideo Ito, "Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA," IEICE Trans. Inf. & Syst., Vol.E96-D, No.8, pp.1613-1623, Aug. 2013.
  16. Kazuteru Namba and Hideo Ito, "Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits," IEEE Trans. Comput., Vol.60, No.10, pp.1459-1470, Oct. 2011.
  17. Kazuteru Namba and Hideo Ito, "Construction of BILBO FF with Soft-Error-Tolerant Capability," IEICE Trans. Inf. & Syst., Vol.E94-D, No.5, pp.1045-1050, May, 2011.
  18. Kazuteru Namba and Hideo Ito, "Chiba Scan Delay Fault Testing with Short Test Application Time," J. Electronic Test.: Theory & Appl., Vol.26, No.6, pp.667-677, Dec., 2010.
  19. Kazuteru Namba, Kengo Nakashima and Hideo Ito, "Single-Event-Upset Tolerant RS Flip-Flop with Small Area," IEICE Trans. Inf. & Syst., Vol.E93-D, No.12, pp.3407-3409, Dec., 2010.
  20. Kazuteru Namba, Takashi Ikeda and Hideo Ito, "Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing," IEEE Trans. Very Large Scale Integr. Syst., Vol.18, No.9, pp.1265-1276, Sep., 2010.
  21. Kazuteru Namba and Hideo Ito, "Analysis of Path Delay Fault Testability for Two- Rail Logic Circuits," IEICE Trans. Fundamentals, Vol.E92-A, No.9, pp.2295-2303, Sep., 2009.
  22. Kazuteru Namba, Yoshikazu Matsui and Hideo Ito, "Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding," J. Electronic Test.: Theory & Appl., Vol. 25, No. 1, pp.97-105, Feb., 2009.
  23. Kazuteru Namba and Hideo Ito, "Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding," IEICE Trans. Inf. & Syst., Vol.E92-D, No.2, pp.269-282, Feb., 2009.
  24. Kazuteru Namba and Hideo Ito, "Redundant Design for Wallace Multiplier," IEICE Trans. Inf. & Syst. Vol.E89-D, No. 9, pp.2512-2524, Sept., 2006.
  25. Kazuteru Namba and Hideo Ito, "Proposal of Testable Multi-Context FPGA Architecture," IEICE Trans. Inf. & Syst. Vol.E89-D, No. 5, pp.1687-1693, May, 2006.
  26. Kazuteru Namba and Hideo Ito, "Scan Design for Two-Pattern Test without Extra Latches," IEICE Trans. Inf. & Syst. Vol.E88-D, No. 12, pp.2777-2785, Dec., 2005.
  27. Kazuteru Namba and Hideo Ito, "Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation," IEICE Trans. Inf. & Syst. Vol.E88-D, No. 9, pp.2135-2142, Sept., 2005.
  28. (*) 難波 一輝, "2段階バースト/ビット誤り訂正機能を有する不均一誤り制御符号," 信学論 A, Vol.J86-A, No. 5, pp.578-586, 2003年 5月.
  29. (*) 難波 一輝, 藤原 英二, "整数環上で構成した多元1シンボル誤り訂正・隣接2シンボル入れ換え誤り訂正符号," 信学論 D-I, Vol.J86-D-I, No.1, pp.23-28, 2003年 1月.
  30. Kazuteru Namba and Eiji Fujiwara, "Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities," IEICE Trans. Fundamentals, Vol.E85-A, No.6, pp.1426-1430, June, 2002.
  31. (*) 難波 一輝, 藤原 英二, "多元単一シンボル誤り訂正符号," 信学論 D-I, Vol.J83-D-I, No.3, pp.368-374, 2000年 3月.

連名 (院生・学生が筆頭)

  1. Yuta Yamamoto and Kazuteru Namba, "Complete double node upset tolerant latch using C-element," IEICE Trans. Inf. & Syst. (掲載予定).
  2. Ri Cui and Kazuteru Namba, "A Calibration Technique for DVMC with Delay Time Controllable Inverter," IPSJ Trans. Syst. LSI Des. Method, Vol.9, pp.30-36, Feb. 2016.
  3. Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion," IEICE Trans. Inf. & Syst., Vol.E97-D, No.10, pp.2719-2729, Oct. 2014.
  4. Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement," IEICE Trans. Inf. & Syst., Vol.E97-D, No.3, pp.533-540, Mar. 2014.
  5. Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF," IEICE Trans. Inf. & Syst., Vol.E96-D, No.5, pp.1219-1222, May, 2013.
  6. Kiyonori Matsumoto, Kazuteru Namba and Hideo Ito, "Scan FF Reordering for Test Volume Reduction in Chiba-Scan Architecture," IPSJ Trans. Syst. LSI Des. Method, Vol.4, pp.140-149, Aug., 2011.
  7. 田辺 融, 加藤 健太郎, 難波 一輝, 伊藤 秀男, "差分によるVLSI回路の遅延測定," 信学論 D, Vol.J93-D, No.4, pp.460-468, 2010年 4月.
  8. Shuangyu Ruan, Kazuteru Namba and Hideo Ito, "Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability," IEICE Trans. Inf. & Syst., Vol.E92-D, No.8, pp.1534-1541, Aug., 2009.
  9. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths," IEICE Trans. Inf. & Syst., Vol.E92-D, No.3, pp.433-442, Mar., 2009.
  10. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Design for Delay Fault Testability of 2-Rail Logic Circuits," IEICE Trans. Inf. & Syst., Vol.E92-D, No.2, pp.336-341, Feb., 2009.
  11. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability," IPSJ Trans. Syst. LSI Des. Method, Vol. 1, pp.91-103, Aug., 2008.
  12. Yoichi Sasaki, Kazuteru Namba and Hideo Ito, "Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger," J. Electronic Test.: Theory & Appl. Vol.24, No.1-3, pp.11-19, June, 2008.

連名 (その他)

  1. Wei Wei, Kazuteru Namba, Yong-Bin Kim and Fabrizio Lombardi, "A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories, " IEEE Trans. Comput., vol. 65, no. 3, pp.781-790, Mar. 2016.
  2. Wei Wei, Kazuteru Namba, Jie Han and Fabrizio Lombardi, "Design of a Non-Volatile 7T1R SRAM Cell for Instant-on Operation," IEEE Trans. Nanotechnol., vol. 13, no. 5, pp. 905-916, Sep. 2014.
  3. Wei Wei, Kazuteru Namba and Fabrizio Lombardi, "Extending Non-Volatile Operation to DRAM Cells," IEEE Access, vol. 1, pp. 758-769, Nov. 2013.
  4. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection, " IEEE Trans. Very Large Scale Integr. Syst., vol. 20, No. 5, pp.804-817, May 2012.
  5. (*) 藤原 英二, 難波 一輝, 北神 正人, "バースト誤り制御符号に対する並列復号法," 信学論 A, Vol.J85-A, No.11, pp.1284-1295, 2002年 11月.

(*) の付いている論文については Electronics and Communications in JAPAN 誌に英訳があります。

国際会議 (査読付き)

筆頭

院生・学生による発表

その他の発表

研究会・全国大会

筆頭

院生・学生による発表

その他の発表

特許

権利化済

出願中・取り下げ済

その他

謝辞

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リンク

北神・難波研究室
情報画像学科
工学部
千葉大学


居室

西千葉キャンパス工学部1号棟4階411号室 (内線:3255)

オフィスアワー

平日10:00-17:00
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予め連絡の上来室のこと

namba@ieee.org