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1. Kazuteru Namba, "Master-slave FF using DICE capable of tolerating soft errors occurring around clock edge, " IEICE Trans. Inf. & Syst., (·ÇºÜͽÄê).
2. Kazuteru Namba and Fabrizio Lombardi, "Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)," IEEE Trans. Comput. Vol.68, No.2, pp.301-306, Feb. 2019.
3. Kazuteru Namba and Fabrizio Lombardi, "A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits," IEEE Trans. Comput. Vol.67, No.10, pp.1525-1531, Oct. 2018.
4. Kazuteru Namba and Fabrizio Lombardi, "On coding for endurance enhancement and error control of phase change memories (PCMs) with write latency reduction," IEEE Trans. Very Large Scale Integr. Syst., Vol.26, No.2, pp.230-238, Feb. 2018.
5. Kazuteru Namba and Fabrizio Lombardi, "Parallel decodable multi-level unequal burst error correcting codes for memories of approximate systems," IEEE Trans. Comput., Vol.65, No.12, pp.3794-3801, Dec. 2016.
6. Kazuteru Namba and Fabrizio Lombardi, "A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems," IEEE Trans. Multi-Scale Comput. Syst., Vol.2, No.4, pp.291-296, Sep. 2016.
7. Kazuteru Namba and Fabrizio Lombardi, "Single multiscale-symbol error correction codes for multiscale storage systems," IEEE Trans. Comput., Vol. 65, No. 6, pp.2005-2009, Jun 2016.
8. Kazuteru Namba and Fabrizio Lombardi, "High-speed parallel decodable non-binary single-error correcting (SEC) codes," IEEE Trans. Device Mater. Reliab., Vol. 16, No. 1, pp.30-37, Mar. 2016.
9. Kazuteru Namba and Fabrizio Lombardi, "Parallel decodable two-level unequal burst error correcting codes," IEEE Trans. Comput., Vol. 64, No. 10, pp. 2902-2911, Oct. 2015.
10. Kazuteru Namba and Fabrizio Lombardi, "Non-binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)," IEEE Trans. Comput., Vol. 64, No. 7, pp.2092-2097, Jul. 2015.
11. Kazuteru Namba and Fabrizio Lombardi, "A single and adjacent symbol error correcting parallel decoder for Reed-Solomon codes," IEEE Trans. Device Mater. Reliab., Vol. 15, No. 1, pp.75-81, Mar. 2015.
12. Kazuteru Namba, Salvatore Pontarelli, Marco Ottavi and Fabrizio Lombardi, "A single-bit and double-adjacent error correcting parallel decoder for multiple-bit error correcting BCH codes," IEEE Trans. Device Mater. Reliab., Vol.14, No.2, pp.664-671, Jun. 2014.
13. Kazuteru Namba and Fabrizio Lombardi, "Concurrent Error Detection of Binary and non-Binary OLS Parallel Decoders," IEEE Trans. Device Mater. Reliab. Vol.14, No.1, pp.112-120, Mar. 2014.
14. Kazuteru Namba, Takashi Katagiri and Hideo Ito, "Timing-error-detecting Dual-edge-triggered Flip-flop," J. Electronic Test.: Theory & Appl., Vol.29, No.4, pp.545-554, Aug. 2013.
15. Kazuteru Namba, Nobuhide Takashina and Hideo Ito, "Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA," IEICE Trans. Inf. & Syst., Vol.E96-D, No.8, pp.1613-1623, Aug. 2013.
16. Kazuteru Namba and Hideo Ito, "Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits," IEEE Trans. Comput., Vol.60, No.10, pp.1459-1470, Oct. 2011.
17. Kazuteru Namba and Hideo Ito, "Construction of BILBO FF with Soft-Error-Tolerant Capability," IEICE Trans. Inf. & Syst., Vol.E94-D, No.5, pp.1045-1050, May, 2011.
18. Kazuteru Namba and Hideo Ito, "Chiba Scan Delay Fault Testing with Short Test Application Time," J. Electronic Test.: Theory & Appl., Vol.26, No.6, pp.667-677, Dec., 2010.
19. Kazuteru Namba, Kengo Nakashima and Hideo Ito, "Single-Event-Upset Tolerant RS Flip-Flop with Small Area," IEICE Trans. Inf. & Syst., Vol.E93-D, No.12, pp.3407-3409, Dec., 2010.
20. Kazuteru Namba, Takashi Ikeda and Hideo Ito, "Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing," IEEE Trans. Very Large Scale Integr. Syst., Vol.18, No.9, pp.1265-1276, Sep., 2010.
21. Kazuteru Namba and Hideo Ito, "Analysis of Path Delay Fault Testability for Two- Rail Logic Circuits," IEICE Trans. Fundamentals, Vol.E92-A, No.9, pp.2295-2303, Sep., 2009.
22. Kazuteru Namba, Yoshikazu Matsui and Hideo Ito, "Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding," J. Electronic Test.: Theory & Appl., Vol. 25, No. 1, pp.97-105, Feb., 2009.
23. Kazuteru Namba and Hideo Ito, "Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding," IEICE Trans. Inf. & Syst., Vol.E92-D, No.2, pp.269-282, Feb., 2009.
24. Kazuteru Namba and Hideo Ito, "Redundant Design for Wallace Multiplier," IEICE Trans. Inf. & Syst. Vol.E89-D, No. 9, pp.2512-2524, Sept., 2006.
25. Kazuteru Namba and Hideo Ito, "Proposal of Testable Multi-Context FPGA Architecture," IEICE Trans. Inf. & Syst. Vol.E89-D, No. 5, pp.1687-1693, May, 2006.
26. Kazuteru Namba and Hideo Ito, "Scan Design for Two-Pattern Test without Extra Latches," IEICE Trans. Inf. & Syst. Vol.E88-D, No. 12, pp.2777-2785, Dec., 2005.
27. Kazuteru Namba and Hideo Ito, "Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation," IEICE Trans. Inf. & Syst. Vol.E88-D, No. 9, pp.2135-2142, Sept., 2005.
28. (*) ÆñÇÈ °ìµ±, "2Ãʳ¬¥Ð¡¼¥¹¥È/¥Ó¥Ã¥È¸í¤êÄûÀµµ¡Ç½¤òÍ­¤¹¤ëÉԶѰì¸í¤êÀ©¸æÉä¹æ," ¿®³ØÏÀ A, Vol.J86-A, No. 5, pp.578-586, 2003ǯ 5·î.
29. (*) ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "À°¿ô´Ä¾å¤Ç¹½À®¤·¤¿Â¿¸µ1¥·¥ó¥Ü¥ë¸í¤êÄûÀµ¡¦ÎÙÀÜ2¥·¥ó¥Ü¥ëÆþ¤ì´¹¤¨¸í¤êÄûÀµÉä¹æ," ¿®³ØÏÀ D-I, Vol.J86-D-I, No.1, pp.23-28, 2003ǯ 1·î.
30. Kazuteru Namba and Eiji Fujiwara, "Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities," IEICE Trans. Fundamentals, Vol.E85-A, No.6, pp.1426-1430, June, 2002.
31. (*) ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "¿¸µÃ±°ì¥·¥ó¥Ü¥ë¸í¤êÄûÀµÉä¹æ," ¿®³ØÏÀ D-I, Vol.J83-D-I, No.3, pp.368-374, 2000ǯ 3·î.

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32. Yuta Yamamoto and Kazuteru Namba, "Complete double node upset tolerant latch using C-element," IEICE Trans. Inf. & Syst. (·ÇºÜͽÄê).
33. Ri Cui and Kazuteru Namba, "A Calibration Technique for DVMC with Delay Time Controllable Inverter," IPSJ Trans. Syst. LSI Des. Method, Vol.9, pp.30-36, Feb. 2016.
34. Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion," IEICE Trans. Inf. & Syst., Vol.E97-D, No.10, pp.2719-2729, Oct. 2014.
35. Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement," IEICE Trans. Inf. & Syst., Vol.E97-D, No.3, pp.533-540, Mar. 2014.
36. Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF," IEICE Trans. Inf. & Syst., Vol.E96-D, No.5, pp.1219-1222, May, 2013.
37. Kiyonori Matsumoto, Kazuteru Namba and Hideo Ito, "Scan FF Reordering for Test Volume Reduction in Chiba-Scan Architecture," IPSJ Trans. Syst. LSI Des. Method, Vol.4, pp.140-149, Aug., 2011.
38. ÅÄÊÕ Í», ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "º¹Ê¬¤Ë¤è¤ëVLSI²óÏ©¤ÎÃÙ±ä¬Äê," ¿®³ØÏÀ D, Vol.J93-D, No.4, pp.460-468, 2010ǯ 4·î.
39. Shuangyu Ruan, Kazuteru Namba and Hideo Ito, "Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability," IEICE Trans. Inf. & Syst., Vol.E92-D, No.8, pp.1534-1541, Aug., 2009.
40. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths," IEICE Trans. Inf. & Syst., Vol.E92-D, No.3, pp.433-442, Mar., 2009.
41. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Design for Delay Fault Testability of 2-Rail Logic Circuits," IEICE Trans. Inf. & Syst., Vol.E92-D, No.2, pp.336-341, Feb., 2009.
42. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability," IPSJ Trans. Syst. LSI Des. Method, Vol. 1, pp.91-103, Aug., 2008.
43. Yoichi Sasaki, Kazuteru Namba and Hideo Ito, "Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger," J. Electronic Test.: Theory & Appl. Vol.24, No.1-3, pp.11-19, June, 2008.

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44. Wei Wei, Kazuteru Namba, Yong-Bin Kim and Fabrizio Lombardi, "A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories, " IEEE Trans. Comput., vol. 65, no. 3, pp.781-790, Mar. 2016.
45. Wei Wei, Kazuteru Namba, Jie Han and Fabrizio Lombardi, "Design of a Non-Volatile 7T1R SRAM Cell for Instant-on Operation," IEEE Trans. Nanotechnol., vol. 13, no. 5, pp. 905-916, Sep. 2014.
46. Wei Wei, Kazuteru Namba and Fabrizio Lombardi, "Extending Non-Volatile Operation to DRAM Cells," IEEE Access, vol. 1, pp. 758-769, Nov. 2013.
47. Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection, " IEEE Trans. Very Large Scale Integr. Syst., vol. 20, No. 5, pp.804-817, May 2012.
48. (*) Æ£¸¶ ±ÑÆó, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, "¥Ð¡¼¥¹¥È¸í¤êÀ©¸æÉä¹æ¤ËÂФ¹¤ëÊÂÎóÉü¹æË¡," ¿®³ØÏÀ A, Vol.J85-A, No.11, pp.1284-1295, 2002ǯ 11·î.

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• Kazuteru Namba and Fabrizio Lombardi, "A Novel Scheme for Concurrent Error Detection of OLS Parallel Decoders," Proc. 2013 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., pp.52-57, Oct. 2013.
• Kazuteru Namba, Nobuhide Takashina and Hideo Ito, "Delay Measurement of Global Routing Resources in FPGA for Small Delay Defect Detection," Proc. 13th IEEE Workshop RTL & High Level Test., pp.4.4.1-4.4.6, Nov., 2012.
• Kazuteru Namba, Takashi Katagiri and Hideo Ito, "Dual-Edge-Triggered FF with Timing Error Detection Capability, " Proc. 2012 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., pp.187-192, Oct., 2012.
• Kazuteru Namba and Hideo Ito, "Soft Error Tolerant BILBO FF," Proc. 25th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.73-81, Oct., 2010.
• Kazuteru Namba, Masatoshi Sakata and Hideo Ito, "Single Event Induced Double Node Upset Tolerant Latch," Proc. 25th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.280-288, Oct. 2010.
• Kazuteru Namba and Hideo Ito, "Path Delay Fault Test Set for Two-Rail Logic Circuits," Proc. 14th IEEE Int'l Symp. Pacific Rim Dependable Comput., pp.347-348, Dec., 2008.
• Kazuteru Namba and Hideo Ito, "Delay Fault Testability on Two-Rail Logic Circuits," Proc. 23rd IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.482-490, Oct., 2008.
• Kazuteru Namba, Yoshikazu Matsui and Hideo Ito, "Improvement in Test Compression for IP Core Testing Using Reconfigurable Network," Proc. 8th IEEE Workshop RTL & High Level Test., pp.61-66, Oct., 2007.
• Kazuteru Namba and Hideo Ito, "Interleaving of Delay Fault Test Data for Efficient Test Compression with Statistical Coding," Proc. 15th IEEE Asian Test Symp., pp.389-394, Nov., 2006.
• Kazuteru Namba and Hideo Ito, "Design of Defect Tolerant Wallace Multiplier," Proc. 11th IEEE Int'l Symp. Pacific Rim Dependable Comput., pp.300-304, Dec., 2005.
• Kazuteru Namba and Eiji Fujiwara, "Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities," Proc. 16th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.299-307, Oct., 2001.

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• Tomohiro Takahashi and Kazuteru Namba, "Influence of recognition performance on recurrent neural network using phase-change memory as synapses," Proc IEEE Int'l Conf. Consum. Electron. Taiwan, Sept. 2020 (ȯɽͽÄê).
• Yuta Yamamoto and Kazuteru Namba, "Construction of latch design with complete double node upset tolerant capability using C-element," Proc. 2018 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., Oct. 2018.
• Nao Horita and Kazuteru Namba, "Measurements of critical charge around rising edge of clock signal," Proc IEEE Int'l Conf. Consum. Electron. Taiwan, May 2018.
• Hiroki Ueno and Kazuteru Namba, "Construction of A Soft Error (SEU) Hardened Latch with High Critical Charge," Proc. 2016 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., pp.27-30, Sep. 2016.
• Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Area Overhead Reduction for Small-Delay Defect Detection Using On-chip Delay Measurement, " Proc. IEEE 12th Int'l Conf. Solid-State & Integr. Circuit Technol., Oct. 2014.
• Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Delay Measurement of Dual-Rail Asynchronous Circuits for Small-Delay Defect Detection, " Proc. IEEE Tencon 2013, Oct. 2013.
• Kouta Maebashi, Kazuteru Namba and Masato Kitakami, "Testing of switch blocks in TSV-reduced three-dimensional FPGA," Proc. 2013 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., pp.302-307, Oct. 2013.
• Takieddine Sbiai and Kazuteru Namba, "NoC Dynamically Reconfigurable as TAM, " Proc. 21st IEEE Asian Test Symp., pp.326-331, Nov., 2012.
• Wenpo Zhang, Kazuteru Namba and Hideo Ito, "Improving Small-Delay Fault Coverage for On-chip Delay Measurement, " Proc. 2012 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., pp.193-198, Oct., 2012.
• Kiyonori Matsumoto, Kazuteru Namba and Hideo Ito, "Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability," Proc. 11th IEEE Workshop RTL & High Level Test., pp.111-116, Dec., 2010.
• Takumi Hoshi, Kazuteru Namba and Hideo Ito, "Testing of Switch Blocks in Three-Dimensional FPGA," Proc. 24th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.227-235, Oct., 2009.
• Shuangyu Ruan, Kazuteru Namba and Hideo Ito, "Soft Error Hardened FF Capable of Detecting Wide Error Pulse," Proc. 23rd IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.272-280, Oct., 2008.
• Takashi Ikeda, Kazuteru Namba and Hideo Ito, "Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing," Proc. 22nd IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.282-290, Sept., 2007.
• Yoichi Sasaki, Kazuteru Namba and Hideo Ito, "Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit," Proc. 21st IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp.327-335, Oct. 2006.

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• Shanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Livi Xiao, Fabrizio Lombardi, "Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells, " Proc. 2019 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., Oct. 2019.
• Josaphat Tetuko Sri Sumantyo, Nobuyoshi Imura, Shunsuke Onishi, Tetsuo Yasaka, Robertus Heru Triharjanto and Koichi Ito, Steven Gao, Kazuteru Namba, Katsumi Hattori, Fumio Yamazaki, Chiharu Hongo, Akira Kato, Daniele Perissin, "L-band Circularly Polarized SAR onboard Microsatellite," Proc. IEEE Int'l Geosci. Remote Sens. Symp., Jul. 2017.
• Wei Wei, Kazuteru Namba and Fabrizio Lombardi "Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level, " Proc. 26th ACM Int'l Conf. Great Lakes Symp. VLSI, pp. 125-128, May. 2016.
• Wei Wei, Kazuteru Namba and Fabrizio Lombardi, "Hybrid Designs for Non-Volatile Embedded Memory Cells," Proc. IEEE 15th Int'l Conf. Nanotechnol., pp.1206-1209, Jul. 2015.
• Fabrizio Lombardi, Wei Wei and Kazuteru Namba, "Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits, " Proc. 25th ACM Int'l Conf. Great Lakes Symp. VLSI, pp. 91-94, May. 2015.
• Wei Wei, Kazuteru Namba and Fabrizio Lombardi, "Designs and Analysis of Non-Volatile Memory Cells for Single Event Upset (SEU) Tolerance," Proc. 2014 IEEE Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnol. Syst., pp.69-74, Oct. 2014.
• Wei Wei, Kazuteru Namba and Fabrizio Lombardi, "New 4T-Based DRAM Cell Designs," Proc. 24th ACM Int'l Conf. Great Lakes Symp. VLSI, pp.199-204, May 2014.
• Masato Kitakami, Hiroshi Konno, Kazuteru Namba and Hideo Ito, "Quantitative Evaluation of Integrity for Remote System Using the Internet," Proc. 16th IEEE Int'l Symp. Pacific Rim Dependable Comput., pp.229-230, Dec., 2010.
• Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "A Low Area On-Chip Delay Measurement System Using Embedded Delay Measurement Circuit," Proc. 19th IEEE Asian Test Symp., pp.343-348, Dec., 2010.
• Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "A Low-Area and Short-Time Scan-Based Embedded Delay Measurement Using Signature Registers," Proc. IEEE Int'l Symp. VLSI Des., Autom. & Test, pp.311-314, Apr., 2010.
• Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba and Hideo Ito, "A Delay Measurement Technique Using Signature Registers," Proc. 18th IEEE Asian Test Symp., pp.161-166, Nov., 2009.
• Masato Kitakami, Akihiro Katada, Kazuteru Namba and Hideo Ito, "Dependability Evaluation for Internet-based Remote Systems," Proc. 15th IEEE Int'l Symp. Pacific Rim Dependable Comput., pp.256-259, Nov., 2009.
• Eiji Fujiwara, Kazuteru Namba, and Masato Kitakami, "Parallel Decoding for Burst Error Control Codes," Proc. 2002 IEEE Int. Symp. Information Theory, p.429, June, 2002.

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• ÆñÇÈ °ìµ±, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á¤Ë¤ª¤±¤ë¥»¥Ã¥È¥¢¥Ã¥×¥Û¡¼¥ë¥É»þ´Ö¤ÈÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤Î´Ø·¸," ¿®³Øµ»Êó, FIIS, 2019ǯ 10·î.
• ÆñÇÈ °ìµ±, ¾åÌî ¹°µ®, "°Û¤Ê¤ëÅŸ»ÅÅ°µ¤ËÂФ¹¤ëÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¥é¥Ã¥Á²óÏ©¤Ø¤ÎÃæÀ­»ÒÀþ¾È¼Í¼Â¸³," ¿®³Øµ»Êó, FIIS, 2019ǯ 3·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥½¥Õ¥È¥¨¥é¡¼ÄûÀµµ¡Ç½¤òÍ­¤¹¤ëBILBO¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×," ¿®³Øµ»Êó, DC2010-4, 2010ǯ 4·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½SEH¥é¥Ã¥Á¤Ë¤ª¤±¤ë¥¨¥ó¥Ï¥ó¥¹¥É¥¹¥­¥ã¥ó¥Æ¥¹¥È," ¿®³Øµ»Êó, FIIS, 2008ǯ 10·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "2Àþ¼°ÏÀÍý²óÏ©¤ËÂФ¹¤ë¥Ñ¥¹ÃÙ±ä¸Î¾ã¥Æ¥¹¥È½¸¹ç," ¿®³Øµ»Êó, FIIS, 2008ǯ 3·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "2Àþ¼°ÏÀÍý²óÏ©¤Ë¤ª¤±¤ëÃÙ±ä¸Î¾ã¥Æ¥¹¥È," ¿®³Øµ»Êó, FIIS, 2007ǯ 10·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "·ç´ÙµßºÑWallace¾è»»´ï¤ÎÀß·×," ¿®³Øµ»Êó, FIIS, 2005ǯ 6·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¾éĹ¥é¥Ã¥Á¤òÍ­¤µ¤Ê¤¤2¥Ñ¥¿¡¼¥ó¥Æ¥¹¥ÈÍÑ¥¹¥­¥ã¥óÀß·×," FTC, 2005ǯ 1·î.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "SoC¤Î¶É½ê¥Û¥â¥¸¡¼¥Ë¥¢¥¹·ç´ÙµßºÑÊý¼°," FTC, 2004ǯ 7·î.
• ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "Æþ¤ì´¹¤¨¸í¤êÀ©¸æµ¡Ç½¤òÍ­¤¹¤ë¿¸µÉԶѰì¸í¤êÀ©¸æÉä¹æ," ¿®³Ø'02ÁíÂç, D-10-1, 2002ǯ.
• ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "¥Ð¡¼¥¹¥È¸í¤ê¤ËÂФ¹¤ëÊݸǽ¤òÍ­¤¹¤ë1¥Ó¥Ã¥È¸í¤êÄûÀµÉä¹æ¤Î¹½À®Ë¡," ¿®³Ø'00¥½Âç, D-10-1, 2000ǯ.
• ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "ÉԶѰì¥Ð¡¼¥¹¥È¸í¤êÊݸǽ¤òÍ­¤¹¤ë1¥Ó¥Ã¥È¸í¤êÄûÀµÉä¹æ," ¿®³Ø'99ÁíÂç, D-10-9, 1999ǯ.
• ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "¥Ð¡¼¥¹¥È¸í¤ê¤ËÂФ¹¤ëÊݸǽ¤òÍ­¤¹¤ëñ°ì¥Ó¥Ã¥È¸í¤êÄûÀµÉä¹æ," ¿®³Øµ»Êó, FTS99-67, pp.15-22, 1999ǯ.
• ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "¥Ð¡¼¥¹¥È¸í¤ê¤ËÂФ¹¤ëÊݸǽ¤òÍ­¤¹¤ëSECÉä¹æ," ¿®³Ø'98ÁíÂç, A-6-16, 1998ǯ.
• ÆñÇÈ °ìµ±, Æ£¸¶ ±ÑÆó, "À°¿ô´Ä¾å¤Ç¹½À®¤·¤¿Ã±°ì¥·¥ó¥Ü¥ë¸í¤êÄûÀµÉä¹æ," ¿®³Ø'97¥½Âç, A-6-3, 1997ǯ.

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• ¼¼²ì ¸µÀ², ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "FPGA¤òÍѤ¤¤¿CP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à´ðÈĤÎÀß·×," ¿®³Øµ»Êó, SANE, 2020ǯ 11·î (ȯɽͽÄê).
• Haijia Xu, Kazuteru Namba, "DET Flip-Flops with SEU Detection Capability Using DICE and C-Element," ¿®³Øµ»Êó, DC, 2020ǯ 11·î (ȯɽͽÄê).
• ÍÌ ÚßÅ·, ÆñÇÈ °ìµ±, "ÁêÊѲ½¥á¥â¥ê¤òÍѤ¤¤¿ÀÖ¹õÌÚ¹½Â¤¤Î½ñ¤­¹þ¤ß»þ´Öºï¸º," ¿®³Øµ»Êó, FIIS, 2020ǯ 10·î (ȯɽͽÄê).
• ÃæÅÄ °Ô¿á, ÆñÇÈ °ìµ±, "C-element¤òÍѤ¤¤¿ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤òÍ­¤¹¤ëSR¥é¥Ã¥Á," ¿®³Øµ»Êó, DC, 2020ǯ 10·î (ȯɽͽÄê).
• Íû ´ä, ÆñÇÈ °ìµ±, "FPGA¾å¤Ç¤Î°Û¤Ê¤ë¥Ó¥Ã¥È¿ô¥·¥Ê¥×¥¹½Å¤ß¤ËÁêÊѲ½¥á¥â¥ê¤òÍѤ¤¤¿¾ö¤ß¹þ¤ß¥Ë¥å¡¼¥é¥ë¥Í¥Ã¥È¥ï¡¼¥¯," ¿®³Øµ»Êó, FIIS, 2020ǯ 3·î.
• ¹â¶¶ Ãι¨, ÆñÇÈ °ìµ±, "½Å¤ßÊݸ¤ËÁêÊѲ½¥á¥â¥ê¤òÍѤ¤¤¿¾ì¹ç¤Î¥ê¥«¥ì¥ó¥È¥Ë¥å¡¼¥é¥ë¥Í¥Ã¥È¥ï¡¼¥¯¤Ø¤Î¼±ÊÌÀ­Ç½¤Î±Æ¶Á," ¿®³Øµ»Êó, FIIS, 2020ǯ 3·î.
• »³ËÜ ÍºÂÀ, ÆñÇÈ °ìµ±, "C-element¤òÍѤ¤¤¿ÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á¤Ë¤ª¤±¤ëÅŸ»ÅÅ°µ¤ÈÎ׳¦ÅŲÙÎ̤δط¸," FTC¸¦µæ²ñ, 2020ǯ 1·î.
• ÃæÅÄ °Ô¿á, »³ËÜ ÍºÂÀ, ËÙÅÄ Æà±û, ÆñÇÈ °ìµ±, "ÃæÀ­»ÒÀþ¾È¼Í¼Â¸³¤Ë¤è¤ë°Û¤Ê¤ë¥²¡¼¥ÈÉý¤òÍ­¤¹¤ëÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á²óÏ©¤Îɾ²Á," ¿®³Øµ»Êó, FIIS, 2019ǯ 6·î.
• É͸ý Ī, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "FPGA¤òÍѤ¤¤¿TCP/IPÄÌ¿®¼ÂÁõCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à," ¿®³Øµ»Êó, FIIS, 2019ǯ 3·î.
• ÄÄ Çݶò, ÆñÇÈ °ìµ±, "¥·¥Ê¥×¥¹½Å¤ß¤ËÁêÊѲ½¥á¥â¥ê¤òÍѤ¤¤¿¥Ë¥å¡¼¥é¥ë¥Í¥Ã¥È¥ï¡¼¥¯¤Î¼±ÊÌÀ­Ç½¤Ø¤Î±Æ¶Á," FTC¸¦µæ²ñ, 2019ǯ 1·î.
• Íû ÍÛ, ÆñÇÈ °ìµ±, "PCM¥·¥Ê¥×¥¹¥Ù¡¼¥¹¤Î¥Ë¥å¡¼¥é¥ë¥Í¥Ã¥È¥ï¡¼¥¯ÍѤÎCPU¤È·ë¹ç¤·¤¿¥¦¥§¥¤¥È¥È¥ì¡¼¥Ë¥ó¥°ÊýË¡," FTC¸¦µæ²ñ, 2019ǯ 1·î.
• »³ËÜ ÍºÂÀ, ÆñÇÈ °ìµ±, "C-element¤òÍѤ¤¤¿DNUÂÑÀ­¥é¥Ã¥Á," ¿®³Øµ»Êó, FIIS, 2018ǯ 6·î.
• ½ù 釗, ÆñÇÈ °ìµ±, "JTAG¤ÈDVMC ¤òÍѤ¤¤¿¥Æ¥¹¥Æ¥£¥ó¥°²óÏ©Àß·×, " ¿®³Øµ»Êó, FIIS, 2018ǯ 6·î.
• Li Dongxu, Kazuteru Namba, "Application of Partial Triple Modular Redundancy (PTMR) in the Wallace-Tree Multiplier," ¿®³Øµ»Êó, FIIS, 2018ǯ 6·î.
• ʸ²° ¾¡, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "¥½¥Õ¥È¥³¥¢CPU¤òÍѤ¤¤¿CP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à," ¿®³Øµ»Êó, FIIS, 2017ǯ 10·î.
• ÄÄ À±±§, ÆñÇÈ °ìµ±, "Cycle-Set Code¡§MLC PCM¤Î½ñ¤­¹þ¤ßÃÙ±ä»þ´Öºï¸º¤Î¤¿¤á¤ÎÉä¹æ," FTC¸¦µæ²ñ, 2017ǯ 7·î.
• ËÙÅÄ Æà±û, ÆñÇÈ °ìµ±, "Delta DICE¤Ë´ð¤Å¤¯Æó½Å¥Î¡¼¥ÉȿžÂÑÀ­¥é¥Ã¥Á²óÏ©," ¿®³Øµ»Êó, FIIS, 2017ǯ 6·î.
• ¾åÌî ¹°µ®, ÆñÇÈ °ìµ±, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¥é¥Ã¥Á²óÏ©¤ËÂФ¹¤ëÃæÀ­»ÒÀþ¾È¼Í¼Â¸³¤ÎÄ´ºº¤Èɾ²Á," ¿®³Øµ»Êó, FIIS, 2017ǯ 6·î.
• ʸ²° ¾¡, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "FPGA¤Ë¤è¤ë¿ÍͤʲèÁü¥µ¥¤¥ºÂбþ¤ÎCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à," ¿®³Øµ»Êó, FIIS, 2016ǯ 6·î.
• ¾åÌî ¹°µ®, ÆñÇÈ °ìµ±, "¹â¤¤ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤òÍ­¤¹¤ë¥é¥Ã¥Á," ¿®³Ø'16ÁíÂç, D-10-1, 2016ǯ 3·î.
• Öà Æü, ÆñÇÈ °ìµ±, "²ÄÊÑÃÙ±äÁǻҤòÍѤ¤¤¿DVMC¤Î³ÓÀµµ»½Ñ¤Îʬ²òǽɾ²Á," FTC¸¦µæ²ñ, 2016ǯ 1·î.
• Öà Æü, ÆñÇÈ °ìµ±, "¥¯¥í¥Ã¥¯È¯À¸´ï¤òÍѤ¤¤¿DVMC¤Î³ÓÀµ," ¿®³Øµ»Êó, FIIS, 2015ǯ 3·î.
• ʸ²° ¾¡, ÈÓÄÍ ·Å, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "UAVÅëºÜCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à¤Ë¤ª¤±¤ë Ethernet¤òÍѤ¤¤¿FPGA´ÖÄÌ¿®," ¿®³Øµ»Êó, FIIS, 2015ǯ 3·î.
• Ä¥ ʸԳ¡¤ÆñÇÈ °ìµ±¡¤°ËÆ£ ½¨ÃË, "¥¹¥­¥ã¥ó²ó¿ôºï¸º¤Ë¤è¤ëÈù¾®ÃÙ±ä¸Î¾ã¬ÄêË¡¤Î¥Æ¥¹¥È°µ½Ì," FTC¸¦µæ²ñ, 2015ǯ1·î.
• Ä¥ ʸԳ¡¤ÆñÇÈ °ìµ±¡¤°ËÆ£ ½¨ÃË, "¥Æ¥¹¥È°µ½Ì¤ò¹Í¤¨¤¿Èù¾®ÃÙ±ä¸Î¾ã¸¡½ÐΨ¸þ¾åË¡," ¿®³Øµ»Êó, FIIS, 2014ǯ 6·î.
• Á°¶¶ ¹§ÂÀ, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, "ÁȤßΩ¤Æ¤ò¹Íθ¤·¤¿TSVºï¸º·¿3¼¡¸µFPGA¤Î¥¹¥¤¥Ã¥Á¥Ö¥í¥Ã¥¯¥Æ¥¹¥È," ¿®³Øµ»Êó, FIIS, 2014ǯ 3·î.
• ÈÓÄÍ ·Å, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "FPGA¤Î¥á¥â¥ê»ÈÍÑÎ̺︺¤Ë¤è¤ëUAVÅëºÜCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à¤Î²þÎÉ," ¿®³Øµ»Êó, FIIS, 2013ǯ 11·î.
• Öà âý, Ä¥ ʸԳ, ÆñÇÈ °ìµ±, "DVMC¤òÍѤ¤¤¿2Àþ¼°ÈóƱ´ü²óÏ©¤ËÂФ¹¤ëÈù¾®ÃÙ±ä¬Äê," ¿®³Ø'13ÁíÂç, D-10-2, 2013ǯ 3·î.
• Á°¶¶ ¹§ÂÀ, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, "TSVºï¸º·¿3¼¡¸µFPGA¤Ë¤ª¤±¤ë¥¹¥¤¥Ã¥Á¥Ö¥í¥Ã¥¯¥Æ¥¹¥È," ¿®³Øµ»Êó, FIIS, 2013ǯ 3·î.
• Áð´Ö Âó¿¿, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "UAVÅëºÜCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à¤ÎVirtex-6 FPGA ¤Ø¤Î¼ÂÁõ," ¿®³Øµ»Êó, SANE2012-114, 2012ǯ 11·î.
• ÅÏîµ ¾ÍÂÀϺ, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, "°Û¼ïº®ºß¥Þ¥ë¥ÁGPU¥·¥¹¥Æ¥à¤Ë¤ª¤±¤ë±é»»¥æ¥Ë¥Ã¥ÈÆÃÀ­¤ò¹Íθ¤·¤¿¥¹¥±¥¸¥å¡¼¥ê¥ó¥°¼êË¡," ¿®³Øµ»Êó, FIIS, 2012ǯ 10·î.
• Ä¥ ʸԳ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥Þ¥ë¥Á¥¹¥­¥ã¥ó¤È¥Æ¥¹¥È¥Ý¥¤¥ó¥ÈÁÞÆþ¤Ë¤è¤ëLOS¤ÎÈù¾®ÃÙ±ä¸Î¾ã¸¡½ÐΨ¸þ¾åË¡," ¿®³Øµ»Êó, FIIS, 2012ǯ 6·î.
• Ì« ¹Àµ×, ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "LOS¤Ë¤è¤ëÈù¾®ÃÙ±ä¸Î¾ã¸¡ºº¤Î¸¡½ÐΨ¸þ¾å¼êË¡," ¿®³Øµ»Êó, FIIS, 2012ǯ 3·î.
• Zhenkun Li, Kentaroh Katoh, Kazuteru Namba, and Hideo Ito, "Improving Small Delay Fault Coverage of LOC by Test Points Insertion," ¿®³Øµ»Êó, FIIS, 2012ǯ 3·î.
• ÎÓ ¾®¿Á, ËÌ¿À Àµ¿Í, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¤¥ó¥¿¡¼¥Í¥Ã¥ÈÍøÍÑ¥·¥¹¥Æ¥à¤Ë¤ª¤±¤ë¹¶·â¤ËÂФ¹¤ë²ÄÍÑÀ­¤ÎÄêÎÌŪɾ²Á," ¿®³Øµ»Êó, FIIS, 2012ǯ 3·î.
• ¹âÉÊ ¿®½¨, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "FPGA¤ÎÇÛÀþ¤Ë¤ª¤±¤ëÈù¾®ÃÙ±ä·ç´Ù¸¡½Ð¤Î¤¿¤á¤ÎÃÙ±ä»þ´Ö¬Äê," FTC, 2012ǯ 1·î.
• ÂçÀÐ ¹Ò»Ö, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, Josaphat Tetuko Sri Sumantyo, "2Ëç¤ÎFPGA¥Ü¡¼¥É¤ÈPC¤ò»ÈÍѤ·¤¿UAVÅëºÜCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à," ¿®³Øµ»Êó, RECONF2011-47, 2011ǯ 11·î.
• Takieddine Sbiai, Kazuteru Namba and Hideo Ito, "A Dynamically Configurable NoC Test Access Mechanism," ¿®³Øµ»Êó, DC2011-36, 2011ǯ 11·î.
• ÀÖÀî ¿µ¿Í, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¹¥­¥ã¥ó¥Á¥§¡¼¥ó¤ÎºÆ¹½À®¤Ë¤è¤ëÀéÍÕÂ祹¥­¥ã¥ó¥Æ¥¹¥È¥Ç¡¼¥¿°µ½Ì¸úΨ¸þ¾å¼êË¡," ¿®³Øµ»Êó, DC2011-48, 2011ǯ 11·î.
• ÊÒ¶Í ¿ò, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¿¥¤¥ß¥ó¥°¥¨¥é¡¼¸¡½Ð²Äǽ¤Ê¥Ç¥å¥¢¥ë¥¨¥Ã¥¸¥È¥ê¥¬FF," ¿®³Øµ»Êó, FIIS, 2011ǯ 11·î.
• Ä¥ ʸԳ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "FF¤Î¿®¹æÄ̲á»þ´Ö¤ò´Þ¤àÈù¾®ÃÙ±ä¥Æ¥¹¥ÈÊý¼°," ¿®³Øµ»Êó, FIIS, 2011ǯ 8·î.
• έ ¸µ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¯¥í¥Ã¥¯¿ôºï¸º¤Ë¤è¤ëÀéÍÕÂ祹¥­¥ã¥óÀ߷פβþÎÉ," FTC, 2011ǯ 7·î.
• À± ¾¢, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "BIST¤Ë¤è¤ë3¼¡¸µFPGA¤Î¥¹¥¤¥Ã¥Á¥Ö¥í¥Ã¥¯¥Æ¥¹¥È," FTC, 2011ǯ 1·î.
• Ê¿ÅÄ ÉÒ¼ù, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, Josaphat Tetuko Sri Sumantyo, "FPGA¤òÍѤ¤¤¿CP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à," ¿®³Øµ»Êó, FIIS, 2010ǯ 10·î.
• ÃæÅç ·ò¸ã, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤òÍ­¤¹¤ëRS¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×," ¿®³Øµ»Êó, FIIS, 2010ǯ 3·î.
• ò² ¾®¶Ñ, ËÌ¿À Àµ¿Í, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "Ê£¿ô¤ÎÇ˲õÍ×ÁǤ«¤é¤ÎƱ»þ¹¶·â¤ò¹Íθ¤·¤¿¥¤¥ó¥¿¡¼¥Í¥Ã¥ÈÍøÍÑ¥·¥¹¥Æ¥à¤Ë¤ª¤±¤ëIntegrity¤ÎÄêÎÌŪɾ²Á," ¿®³Øµ»Êó, FIIS, 2010ǯ 3·î.
• ÅÄÊÕ Í», Ì« ¹Àµ×, ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "º¹Ê¬¤Ë¤è¤ëÃÙ±ä¬ÄêË¡¤Î¼Â¹Ô»þ´Ö¤ÈÌÌÀѤκ︺," ¿®³Øµ»Êó, DC2009-71, 2010ǯ 2·î.
• ¾¾ËÜ À¶µª, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÀéÍÕÂ祹¥­¥ã¥ó¤ÎÀܳ½ç½øÊѹ¹¤Ë¤è¤ë¥Æ¥¹¥È¥Ñ¥¿¡¼¥óºï¸º¼êË¡," FTC, 2010ǯ 1·î.
• ¿ûß· Àµ¹°, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥½¥Õ¥È¥¨¥é¡¼¸¡½Ðµ¡Ç½¤òÍ­¤¹¤ëBILBO¥ì¥¸¥¹¥¿," ¿®³Øµ»Êó, DC2009-37, 2009ǯ 12·î.
• ºäÅÄ ²í½Ó, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥é¥Ã¥ÁÆâ2½Å¥Î¡¼¥Éȿž¥½¥Õ¥È¥¨¥é¡¼¤ÎÂÑÀ­Àß·×," ¿®³Øµ»Êó, FIIS, 2009ǯ 10·î.
• ÅÄÊÕ Í», Haque Md Zahidul, ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "º¹Ê¬¤Ë¤è¤ëVLSI²óÏ©¤ÎÃÙ±ä¬Äê," ¿®³Øµ»Êó, FIIS, 2009ǯ 6·î.
• À± ¾¢, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "3¼¡¸µFPGA¤Ë¤ª¤±¤ë¥¹¥¤¥Ã¥Á¥Ö¥í¥Ã¥¯¤Î¥Æ¥¹¥ÈÊýË¡," ¿®³Øµ»Êó, FIIS, 2009ǯ 3·î.
• ÂçÅç Ë­, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "SRAM·¿FPGA¤ÎLUT¤Ë¤ª¤±¤ëÃÙ±ä¸Î¾ã¸¡½ÐBIST," FTC, 2009ǯ 1·î.
• º£Ìî ¹¨, ËÌ¿À Àµ¿Í, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¤¥ó¥¿¡¼¥Í¥Ã¥ÈÍøÍÑ¥·¥¹¥Æ¥à¤Ë¤ª¤±¤ëIntegrity¤ÎÄêÎÌŪɾ²Á," ¿®³Øµ»Êó, DC2008-63, 2008ǯ 12·î.
• ºäÅÄ ²í½Ó, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥½¥Õ¥È¥¨¥é¡¼Âкö¥é¥Ã¥Á¤ÎÄ´ºº¤ÈʬÎà," ¿®³Øµ»Êó, FIIS, 2008ǯ 6·î.
• ÃæÅç ·ò¸ã, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á¤Î¸¡½ÐÉÔ²Äǽ¤Ê¸ÇÄê¸Î¾ã¤Î±Æ¶Á," ¿®³Øµ»Êó DC2008-8, 2008ǯ 4·î.
• ïö ÁжÌ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "Éý¤Î¹­¤¤¥¨¥é¡¼¥Ñ¥ë¥¹¸¡½Ðµ¡Ç½¤òÍ­¤¹¤ëÂÑ¥½¥Õ¥È¥¨¥é¡¼FF," ¿®³Øµ»Êó DC2008-9, 2008ǯ 4·î.
• ÃÓÅÄ Âî»Ë, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "SEU/SETÂкöFF¤òÍѤ¤¤¿ÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½¥¹¥­¥ã¥ó¹½Â¤," ¿®³Ø'08ÁíÂç, D-10-4, 2008ǯ 3·î.
• »°±º ·ò¹¨, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÆóÀþ¼°ÏÀÍý¤òÍѤ¤¤¿FPGA¤Î¥½¥Õ¥È¥¨¥é¡¼¤ËÂФ¹¤ë¥Õ¥©¡¼¥ë¥È¥»¥­¥å¥¢À­," ¿®³Øµ»Êó, DC2007-74, 2008ǯ 2·î.
• ¶â ³¤±Ñ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¹¥­¥ã¥ó¥¤¥ó¥Ù¥¯¥È¥ëËè¤Ë¥Æ¥¹¥È±þÅú¤ò´Ñ¬¤¹¤ëÃÙ±ä¸Î¾ã¥Æ¥¹¥È," FTC, 2008ǯ 1·î.
• ÊÒ¿ ¾¼Íµ, ËÌ¿À Àµ¿Í, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¤¥ó¥¿¡¼¥Í¥Ã¥ÈÍøÍѱó³Ö¥·¥¹¥Æ¥à¤Î¿®ÍêÀ­É¾²ÁË¡," ¿®³Øµ»Êó, DC2007-60, pp.1-6, 2007ǯ 12·î.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½FFÊý¼°¤Î²¼¤Ç¤Î2Ãʳ¬¥Æ¥¹¥È¥Ç¡¼¥¿°µ½ÌË¡," ¿®³Øµ»Êó DC2007-25, pp.1-6, 2007ǯ 11·î.
• ÂçÅç Ë­, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "SRAM·¿FPGA¤Ë¤ª¤±¤ëLUT¤ÎÃÙ±ä¸Î¾ã¥Æ¥¹¥È," FTC, 2007ǯ 7·î.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½FF¤Ë¤è¤ë½ÌÂà¸Î¾ãÍѥƥ¹¥È¥Ç¡¼¥¿°µ½ÌË¡," ¿®³Øµ»Êó, FIIS, 2007ǯ 6·î.
• ÃÓÅÄ Âî»Ë, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½ÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á¤ÎÀß·×," ¿®³Øµ»Êó, DC2007-1, pp.1-6, 2007ǯ 4·î.
• ¾¾°æ ÎÉÏÂ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ºÆ¹½À®¥¹¥­¥ã¥óʬ´ô¤È¥¨¥ó¥³¡¼¥É¤Ë¤è¤ëIP¥³¥¢¥Æ¥¹¥È¥Ç¡¼¥¿°µ½Ì," ¿®³Øµ»Êó, FIIS, 2007ǯ 3·î.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥Þ¥¹¥¿¤È¥¹¥ì¡¼¥Ö¤Î¥¹¥­¥ã¥ó¥Ñ¥¹¤Ë¤è¤ë¥Æ¥¹¥ÈÍưײ½Àß·×Ë¡," ¿®³Øµ»Êó, FIIS, 2007ǯ 3·î.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "2ÀþÏÀÍý²óÏ©¤ÎÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½Àß·×Ë¡," ¿®³Øµ»Êó, FIIS, 2007ǯ 3·î.
• À±Ìî ÂçÊå, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, °ËÆ£ ½¨ÃË, "¾ðÊó²ÈÅŴ֤οÆÏÂÀ­¡¦¶¥¹çÀ­¤Ë´ð¤Å¤¯Ï¢·ÈÆ°ºî»Ù±ç¼êË¡," ¿®³Øµ»Êó, HIP2006-119, pp.29-34, 2007ǯ 2·î.
• ¶áÆ£ ¿òÇ·, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, °ËÆ£ ½¨ÃË, "TCP¥³¥Í¥¯¥·¥ç¥ó¤Î³ÎΩÍ×µá¤ËÃíÌܤ·¤¿¥ï¡¼¥à¸¡ÃμêË¡," ¿®³Øµ»Êó, CW, 2006ǯ 12·î.
• ²ÃÆ£ ·òÂÀϺ, Õ­ ¶ÌÉÒ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÁÆγÅÙưŪºÆ¹½À®²Äǽ¥Ç¥Ð¥¤¥¹¤ÎPEÉô¥Æ¥¹¥È¤Î¤¿¤á¤ÎDFT," ¿®³Øµ»Êó, DC2006-4, pp.15-24, 2006ǯ 4·î.
• º´¡¹ÌÚ ÍÛ°ì, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥·¥å¥ß¥Ã¥È¥È¥ê¥¬²óÏ©¤òÍѤ¤¤¿¥½¥Õ¥È¥¨¥é¡¼¥Þ¥¹¥¯¥é¥Ã¥Á," ¿®³Ø'06ÁíÂç, D-10-6, 2006ǯ 3·î.
• ±ÝËÜ Í¥Æó, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "½ÌÂà¸Î¾ã¸¡½Ð²Äǽ¤ÊÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á¤ÎÄó°Æ¤Èɾ²Á," ¿®³Øµ»Êó, FIIS, 2006ǯ 3·î.
• ¾®Àô Ȼɧ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "2¥Ñ¥¿¡¼¥ó¥Æ¥¹¥È¥Ç¡¼¥¿°µ½Ì¤È¥Þ¥ë¥Á¥¹¥­¥ã¥óÁàºî," ¿®³Øµ»Êó, FIIS, 2006ǯ 3·î.
• °Ë¿á Ë­, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, °ËÆ£ ½¨ÃË, "¾ðÊ󸡺÷¥µ¡¼¥Ð¤òÍѤ¤¤¿¥Û¡¼¥à¥Í¥Ã¥È¥ï¡¼¥¯¤ÎÀßÄ꼫ư²½¼êË¡," ¿®³Øµ»Êó, CW, 2006ǯ 1·î.
• Àî¸ý ͵ÂÀϺ, ÆñÇÈ °ìµ±, ËÌ¿À Àµ¿Í, °ËÆ£ ½¨ÃË, "RFID¤òÍѤ¤¤¿¾ðÊó²ÈÅÅÁàºî»Ù±ç¥·¥¹¥Æ¥à," ¿®³Øµ»Êó, CW, 2006ǯ 1·î.
• Õ­ ¶ÌÉÒ, ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ưŪºÆ¹½À®²Äǽ¥Ç¥Ð¥¤¥¹¤ÎPEÉô¥Æ¥¹¥È¤Î¤¿¤á¤ÎDFT," FTC, 2006ǯ 1·î.
• ÏÌÞ¼ ÃÒ¹°, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¢¥ë¥´¥ê¥º¥à¤Î²þÎɤˤè¤ëÃÙ±ä¸Î¾ãBIST¤Î²óÏ©Î̺︺," ¿®³Øµ»Êó, FIIS, 2004ǯ10·î.
• ¾®Àô Ȼɧ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "6ÃÍÏÀÍý¤òÍѤ¤¤¿2¥Ñ¥¿¡¼¥ó¥Æ¥¹¥È¥Ç¡¼¥¿¤Î°µ½Ì," ¿®³Øµ»Êó, FIIS, 2004ǯ 6·î.
• ËÜÅÄ ·½°ì, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¾è»»´ï¤Î¾éĹ²½¤Ë¤è¤ë¹âÊâα¤Þ¤ê²½À߷פθ¡Æ¤," ¿®³Øµ»Êó, FIIS, 2004ǯ 3·î.
• ¹â¶¶ ¹§ÂÀ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "·èÄêÏÀŪÃÙ±ä¸Î¾ãBIST¤Î¥Ï¡¼¥É¥¦¥§¥¢Î̺︺ˡ," ¿®³Øµ»Êó, FIIS, 2004ǯ 3·î.
• ½ù ßÛ²¯, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥Æ¥¹¥È¿ô¤ò¾®¤µ¤¯¤·¤¿¥Þ¥ë¥Á¥³¥ó¥Æ¥­¥¹¥ÈFPGA¤Î¸Î¾ã¸¡½Ð," ¿®³Øµ»Êó, FIIS, 2003ǯ 6·î.
• ¹â¶¶ ¹§ÂÀ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥²¡¼¥ÈÆâÍÆÎ̤ò¹Íθ¤·¤¿ÃÙ±ä¸Î¾ã¥Æ¥¹¥È," ¿®³Ø'03ÁíÂç, D-10-12, 2003ǯ 3·î.

¤½¤Î¾¤Îȯɽ

• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¯¥í¥Ã¥¯¿®¹æÍøÍѤΥѥ¹ÃÙ±ä¬Äê¤Ë¤è¤ëÈù¾®ÃÙ±ä¥Æ¥¹¥È," ¿®³Øµ»Êó, FIIS, 2011ǯ 8·î.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "Ä㤤ÌÌÀÑ¥³¥¹¥È¤Î¥ª¥ó¥Á¥Ã¥×Èù¾®ÃÙ±ä¸Î¾ã¸¡½ÐË¡," FIIS, 2010 6·î.
• ²ÃÆ£ ·òÂÀϺ, ÅÄÊÕ Í», Haque Md Zahidul, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥·¥°¥Í¥Á¥ã¥ì¥¸¥¹¥¿¤òÍѤ¤¤¿ÃÙ±ä¬ÄêË¡¡Ý¤½¤Î£², " FTC, 2009ǯ 7·î.
• ²ÃÆ£ ·òÂÀϺ, ÅÄÊÕ Í», Haque Md Zahidul, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥·¥°¥Í¥Á¥ã¥ì¥¸¥¹¥¿¤òÍѤ¤¤¿ÃÙ±ä¬ÄêË¡, " ¿®³Øµ»Êó, FIIS, 2009ǯ 6·î.
• Æ£¸¶ ±ÑÆó, ÆñÇÈ °ìµ±, "¥Ð¡¼¥¹¥È¸í¤êÀ©¸æÉä¹æ¤ËÂФ¹¤ëÊÂÎóÉü¹æË¡," ¿®³Øµ»Êó, FIIS, 2001ǯ.
• Æ£¸¶ ±ÑÆó, ÆñÇÈ °ìµ±, "¥Ð¡¼¥¹¥È¸í¤êÀ©¸æÉä¹æ¤ËÂФ¹¤ëÊÂÎóÉü¹æ," ¿®³Ø'01¥½Âç, D-10-2, 2001ǯ.

Æõö

¸¢Íø²½ºÑ

• Öà Æü, ÆñÇÈ °ìµ±, "ȾƳÂν¸ÀѲóÏ©µÚ¤ÓÃÙ±ä¬Äê²óÏ©," ÆõöÂè6218297¹æ, PCT/JP2016/001185.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©µÚ¤Ó¤½¤ÎÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÊýË¡," Æõö5757550¹æ.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©," Æõö5044778¹æ.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¨¥é¡¼¥È¥ì¥é¥ó¥È¤¬²Äǽ¤ÊȾƳÂν¸ÀѲóÏ©," Æõö4910141¹æ.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©," ÆõöÂè4769951¹æ, PCT/JP2007/053937.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©µÚ¤Ó¤½¤Î¥Æ¥¹¥ÈÊýË¡,"ÆõöÂè4734577¹æ, PCT/JP2007/053835.
• º´¡¹ÌÚ ÍÛ°ì, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥¨¥é¡¼¥È¥ì¥é¥ó¥ÈÊýË¡µÚ¤Ó¤½¤ÎÊýË¡¤ò¼Â¸½²Äǽ¤ÊȾƳÂν¸ÀѲóÏ©," ÆõöÂè4555971¹æ, PCT/JP2007/055342.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©," ÆõöÂè4555968¹æ, U.S. Patent No. 7,945,829, PCT/JP2006/300022.

½Ð´êÃ桦¼è¤ê²¼¤²ºÑ

• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©µÚ¤Ó¤½¤ÎÃÙ±ä¬ÄêÊýË¡," Æôê2009-265825¹æ.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©µÚ¤ÓȾƳÂν¸ÀѲóÏ©¤Î¸¡ººÊýË¡," Æôê2007-233346¹æ.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©," Æôê2007-233388¹æ.
• ÃÓÅÄ Âî»Ë, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ȾƳÂν¸ÀѲóÏ©," Æôê2007-111043¹æ, PCT/JP2008/057637.

¤½¤Î¾

• ÀéÍÕÂç³Ø ÆñÇȸ¦µæ¼¼, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼VLSI¥·¥¹¥Æ¥à ¡Á ²á¹ó¤Ê´Ä¶­²¼¤Ç¤âÆ°ºî¤¹¤ë¥·¥¹¥Æ¥à ¡Á," SEMICON Japan SMART Workforce ¥Ñ¥Ó¥ê¥ª¥ó, 2020.
• ¼¼²ì ¸µÀ², É͸ý Ī, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "UAVÅëºÜCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥àÍѤÎFPGA´ðÈÄÀß·×," Âè22²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2020.
• Noboru Hamaguchi, Kazuteru Namba and Josaphat Tetuko Sri Sumantyo, "CP-SAR Image Processing System using TCP / IP with Kintex-7 FPGA Board, " 9th Indonesia Jpn. Joint Sci. Symp., Nov. 2019.
• ÆñÇÈ °ìµ±, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼VLSI¥·¥¹¥Æ¥à ¡Á ²á¹ó¤Ê´Ä¶­²¼¤Ç¤âÆ°ºî¤¹¤ëIoTÁõÃÖ ¡Á," "¥Ç¥£¥Ú¥ó¥À¥Ö¥ëVLSI¥·¥¹¥Æ¥à ¡Á ¸Î¾ã¤·¤Æ¤âÆ°ºî¤Ç¤­¤ë¹â¿®ÍêIoTÁõÃÖ ¡Á,"»º³Ø¹çƱµ»½Ñ¥·¡¼¥º¸òή²ñ, 2019.
• É͸ý Ī, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "CP-SAR ²èÁü½èÍý¥·¥¹¥Æ¥àÍÑTCP/IPÄÌ¿®´Ä¶­¼ÂÁõ, " ÀéÍÕÂç³ØÂç³Ø±¡¹©³Ø¸¦µæ±¡¥µ¥ÖÎΰèD/F¹çƱ¸¦µæ¥ï¡¼¥¯¥·¥ç¥Ã¥×, 2019
• »³ËÜ ÍºÂÀ, ÆñÇÈ °ìµ±, "C-element¤òÍѤ¤¤¿¥½¥Õ¥È¥¨¥é¡¼ÂÑÀ­¥é¥Ã¥Á¤ÎÄãÅÅ°µÆ°ºî»þ¤Ë¤ª¤±¤ëÎ׳¦²ÙÎ̬Äê," ÀéÍÕÂç³ØÂç³Ø±¡¹©³Ø¸¦µæ±¡¥µ¥ÖÎΰèD/F¹çƱ¸¦µæ¥ï¡¼¥¯¥·¥ç¥Ã¥×, 2019
• É͸ý Ī, ¼¼²ì ¸µÀ², ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "CP-SAR ²èÁü½èÍý¥·¥¹¥Æ¥àÍÑTCP/IPÄÌ¿®´Ä¶­¼ÂÁõ, " Âè21²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2019.
• ¼¼²ì ¸µÀ², É͸ý Ī, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "FPGA¤òÍѤ¤¤¿ CP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à" Ê¿À®30ǯÅÙ¥°¥í¡¼¥Ð¥ë¥×¥í¥ß¥Í¥ó¥È¸¦µæ´ð´´¥·¥ó¥Ý¥¸¥¦¥à, 2018.
• ËÙÅÄ Æà±û, »³ËÜ ÍºÂÀ, ÆñÇÈ °ìµ±, "¥Þ¥ë¥Á¥Ó¥Ã¥È¥¢¥Ã¥×¥»¥Ã¥ÈÂÑÀ­¤òÍ­¤¹¤ë¥é¥Ã¥Á¤Ø¤ÎÊü¼ÍÀþ¾È¼Í¼Â¸³¤Î½àÈ÷," Âè6²ó¥½¥Õ¥È¥¨¥é¡¼(¤Ê¤É¤ÎȾƳÂΤÎÊü¼ÍÀþ¸ú²Ì)ÊÙ¶¯²ñ(¥½¥Õ¥È¥¨¥é¡¼¥ï¡¼¥¯¥·¥ç¥Ã¥×), 2018.
• É͸ý Ī, ʸ²° ¾¡, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "UAVÅëºÜCP-SAR¥·¥¹¥Æ¥à¤Î¤¿¤á¤Î¥×¥ê¥ó¥È´ðÈ×Àß·×, " Âè20²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2018.
• ËÙÅÄ Æà±û, ¹âÅÄ ËãÅÔ, ¾¡Ëô ·¼Æ», ÅçÂÞ ½¨¼ù, ÃæÀî ͺµ®, ¾åÌî ¹°µ®, ÆñÇÈ °ìµ±, "ÃæÀ­»ÒÀþ¾È¼Í¼Â¸³¤Î¤¿¤á¤ÎÂÑ¥½¥Õ¥È¥¨¥é¡¼¥é¥Ã¥Á²óÏ©," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.76, 2017.
• ¾åÌî ¹°µ®, ËÙÅÄ Æà±û, ÆñÇÈ °ìµ±, "DICE¹½Â¤¤ò¸µ¤Ë¤·¤¿ÂÑ¥¨¥é¡¼¥é¥Ã¥Á¤Ø¤ÎÊü¼ÍÀþ¾È¼Í¼Â¸³¤Îɾ²Á," ¥½¥Õ¥È¥¨¥é¡¼(¤Ê¤É¤ÎLSI¤Ë¤ª¤±¤ëÊü¼ÍÀþ¸ú²Ì)¤Ë´Ø¤¹¤ëÂè5²óÊÙ¶¯²ñ, 2017.
• ʸ²° ¾¡, ÆñÇÈ °ìµ±, Josaphat Tetuko Sri Sumantyo, "Kintex-7¤òÍѤ¤¤¿UAVÅëºÜCP-SAR¥·¥¹¥Æ¥à, " Âè19²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2017.
• ÆñÇÈ °ìµ±, "LSI¥Æ¥¹¥ÈÍưײ½À߷פδðÁäÈÃÙ±ä¸Î¾ã¥Æ¥¹¥È¤Î¥Ý¥¤¥ó¥È," ÆüËܥƥ¯¥Î¥»¥ó¥¿¡¼, Feb. 2017.
• ¾åÌî ¹°µ®, ±©ÅÄ Îâ, ÆñÇÈ °ìµ±, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤òÍ­¤¹¤ë¥é¥Ã¥Á²óÏ©," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.69, 2016.
• ÆñÇÈ °ìµ±, "VLSI ¥·¥¹¥Æ¥à¤ÎÁȤ߹þ¤ßÃÙ±ä¬Äê²óÏ©¤È¤½¤Î³ÓÀµË¡," ÀéÍÕ¥¨¥ê¥¢»º³Ø´±Ï¢·È¥ª¡¼¥×¥ó¥Õ¥©¡¼¥é¥à2016.
• Masaru Bunya, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo, "Image Processing System with Kintex-7 FPGA Board," Symp. Innovative Microwave Remote Sens., Nov. 2016.
• Hiroki Ueno and Kazuteru Namba, "Neutron Radiation To Soft Error Hardened Latches, " 7th Indonesia Jpn. Joint Sci. Symp., Nov. 2016.
• ÆñÇÈ °ìµ±, "¹â¿®Íê¾ðÊó¥·¥¹¥Æ¥à¼Â¸½¤Î¤¿¤á¤Î¥Ç¥£¥Ú¥ó¥À¥Ö¥ë¥·¥¹¥Æ¥àLSI," ¥¤¥Î¥Ù¡¼¥·¥ç¥ó¥¸¥ã¥Ñ¥ó Âç³Ø¸«ËÜ»Ô, 2016.
• Masaru Bunya, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo, "CP-SAR processing system on FPGA for multiple image size, " Âè18²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2015.
• ÆñÇÈ °ìµ±, ʸ²° ¾¡, ÈÓÄÍ ·Å, Josaphat Tetuko Sri Sumantyo, "UAVÅëºÜCP-SAR¥·¥¹¥Æ¥à¤Ë¤ª¤±¤ëFPGA´ÖÄÌ¿®¤Î¼ÂÁõ, " Âè17²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2015.
• ÆñÇÈ °ìµ±, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤òÍ­¤¹¤ëVLSI ¥Æ¥¹¥ÈÍưײ½Àß·×, " NIRS¥Æ¥¯¥Î¥Õ¥§¥¢2014.
• ÆñÇÈ °ìµ±, ÈÓÄÍ ·Å, Josaphat Tetuko Sri Sumantyo, "UAVÅëºÜCP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à¤ËÂФ¹¤ëFPGA¤Î¥á¥â¥ê¥ê¥½¡¼¥¹»ÈÍÑÎ̺︺, " Âè16²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2014.
• Kei Iizuka, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo, "Implementation of CP-SAR signal processing system on Virtex-6 FPGA, " Symp. Microsatellites Remote Sensing, Aug. 2013.
• ÆñÇÈ °ìµ±, ÈÓÄÍ ·Å, Áð´Ö Âó¿¿, Josaphat Tetuko Sri Sumantyo, "CP-SAR¿®¹æ½èÍý¥·¥¹¥Æ¥à¤ÎVirtex-6 FPGA¤Ë¤è¤ë¼Â¸½, " Âè15²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2013.
• Takieddine Sbiai, Wenpo Zhang, Kazuteru Namba and Masato Kitakami, "Testing and detecting of faulty links inside the network on chip switches," 5th Indonesia Jpn. Joint Sci. Symp., 2012.
• Kazuteru Namba, Takuma Kusama, Koshi Oishi, Kei Iizuka, Hideo Ito, Josaphat Tetuko Sri Sumantyo, "UAVSAR Processing System with Virtex-6 FPGA Board, " 17th CEReS Int'l Symp., Mar. 2012.
• ÆñÇÈ °ìµ±, Áð´Ö Âó¿¿, ÂçÀÐ ¹Ò»Ö, ÈÓÄÍ ·Å, °ËÆ£ ½¨ÃË, Josaphat Tetuko Sri Sumantyo, "Virtex-6 FPGA¤òÍѤ¤¤¿CP-SAR²èÁü½èÍý¥·¥¹¥Æ¥à, " Âè14²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2012.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "ÂÑ¥½¥Õ¥È¥¨¥é¡¼À­¤òÍ­¤¹¤ëÀ½Â¤¥Æ¥¹¥ÈÍưײ½Àß·×," ¥½¥Õ¥È¥¨¥é¡¼(¤Ê¤É¤ÎLSI¤Ë¤ª¤±¤ëÊü¼ÍÀþ¸ú²Ì)¤Ë´Ø¤¹¤ëÂè1²óÊÙ¶¯²ñ, 2011.
• Koshi Oishi, Kazuteru Namba, Hideo Ito, Josaphat Tetuko Sri Sumantyo, "UAV on-board CP-SAR image processing system using one FPGA board with 2GB DDR3 DRAM, " Int'l Conf. Imaging & Printing Technol., pp.227-230, Aug. 2011.
• ÆñÇÈ °ìµ±, Ê¿ÅÄ ÉÒ¼ù, ÂçÀÐ ¹Ò»Ö, Áð´Ö Âó¿¿, °ËÆ£ ½¨ÃË, Josaphat Tetuko Sri Sumantyo, "Ê£¿ôFPGA¤òÍѤ¤¤¿ UAV-SAR ¿®¹æ½èÍý¥·¥¹¥Æ¥à," Âè13²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2011.
• ÆñÇÈ °ìµ±, Ê¿ÅÄ ÉÒ¼ù, ÂçÀÐ ¹Ò»Ö, °ËÆ£ ½¨ÃË, Josaphat Tetuko Sri Sumantyo, "Ê£¿ôFPGA¤Ë¤è¤ëSAR¿®¹æ½èÍý¥·¥¹¥Æ¥à¤Î¹½ÃÛ," Âè12²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2010.
• À± ¾¢, ¾¾ËÜ À¶µª, Ê¿ÅÄ ÉÒ¼ù, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "RISC·¿CPU¤ÎºîÀ®," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.162, 2009.
• ÆñÇÈ °ìµ±, Ê¿ÅÄ ÉÒ¼ù, °ËÆ£ ½¨ÃË, Bambang Setiadi, Josaphat Tetuko Sri Sumantyo, "¹çÀ®³«¸ý¥ì¡¼¥ÀÅëºÜ¥Þ¥¤¥¯¥í±ÒÀ±ÍÑFFT±é»»FPGA," Âè11²ó´Ä¶­¥ê¥â¡¼¥È¥»¥ó¥·¥ó¥°¥·¥ó¥Ý¥¸¥¦¥à, 2009.
• Toshiki Hirata, Kazuteru Namba, Hideo Ito, Bambang Setiadi, Josaphat Tetuko Sri Sumantyo, "FFT computation FPGA for Microsatellite onboard Synthetic Aperture Radar, " Int'l Workshop Synth. Aperture Radar, Feb. 2009.
• ÀéÍÕÂç³Ø °ËÆ£¡¦ËÌ¿À¡¦ÆñÇȸ¦µæ¼¼, "ÏÀÍý²óÏ©¤ËÂФ¹¤ëÂÑ¥½¥Õ¥È¥¨¥é¡¼Àß·×," ÀéÍÕÂç³Ø¥ª¡¼¥×¥ó¥ê¥µ¡¼¥Á, 2008.
• Kentaroh Katoh, Kazuteru Namba and Hideo Ito, "Design for Delay Fault Testing of 2-Rail Logic Circuits," 3rd Indonesia Jpn. Joint Sci. Symp., 2008.
• ºäÅÄ ²í½Ó, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "CÁǻҤòÍѤ¤¤¿ÂÑ¥½¥Õ¥È¥¨¥é¡¼¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.108, 2008.
• ¿¹ ¹ÌÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥­¥ã¥ê¡¼¥ë¥Ã¥¯¥¢¥Ø¥Ã¥É8¥Ó¥Ã¥È²Ã»»´ï¤ÎºîÀ®," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.108, 2008.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "Æó½Å·Ï²óÏ©¤ËŬ¤·¤¿ÃÙ±ä¸Î¾ã¥Æ¥¹¥ÈÍưײ½Àß·×," ¥­¥ã¥ó¥Ñ¥¹¡¦¥¤¥Î¥Ù¡¼¥·¥ç¥ó¥»¥ó¥¿¡¼Åìµþ ¿·µ»½ÑÀâÌÀ²ñ, 2008.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¹â¿®Íꥷ¥¹¥Æ¥àLSI¤ò¼Â¸½¤¹¤ëÂÑ¥½¥Õ¥È¥¨¥é¡¼¡¦À½Â¤¥Æ¥¹¥ÈÍưײ½Àß·×," Âè2²óÀéÍÕÂç³ØTLOµ»½Ñ°ÜžÆÃÊÌ¥Õ¥§¥¢, 2008.
• ²ÃÆ£ ·òÂÀϺ, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¥Ç¥å¥¢¥ë²óÏ©¡¦ÂÑ¥»¥­¥å¥ê¥Æ¥£²óÏ©¤ÎÃÙ±ä¥Æ¥¹¥ÈÍưײ½," ÀéÍÕÂç³Ø ¿·µ»½ÑÀâÌÀ²ñ, 2008.
• °ËÆ£ ½¨ÃË, ÆñÇÈ °ìµ±, "¹â¿®Íê¾ðÊó¥·¥¹¥Æ¥à¼Â¸½¤Î¤¿¤á¤ÎÂÑ¥½¥Õ¥È¥¨¥é¡¼¥·¥¹¥Æ¥àLSI¤Î³«È¯," ¥¤¥Î¥Ù¡¼¥·¥ç¥ó¥¸¥ã¥Ñ¥ó ¿·µ»½ÑÀâÌÀ²ñ, 2007.
• ïö ÁжÌ, ÂçÅç Ë­, ÃÓÅÄ Âî»Ë, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "±é»»¥æ¥Ë¥Ã¥È²óÏ©PE (Processing Element) ¤Î»îºî," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.148, 2007.
• ÀéÍÕÂç³Ø °ËÆ£¡¦ËÌ¿À¡¦ÆñÇȸ¦µæ¼¼, "ÏÀÍý²óÏ©¤ËÂФ¹¤ëÂÑ¥½¥Õ¥È¥¨¥é¡¼Àß·×," CEATEC JAPAN »º³Ø¸òή¥Ñ¥Ó¥ê¥ª¥ó, 2006.
• ÃÓÅÄ Âî»Ë, Ê¿»³ ¾¡Ç·, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¾éĹ¥é¥Ã¥Á¤òÍ­¤µ¤Ê¤¤2¥Ñ¥¿¡¼¥ó¥Æ¥¹¥ÈÍÑ¥¹¥­¥ã¥óÀ߷ײóÏ©¤Î»îºî," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.210, 2006.
• º´¡¹ÌÚ ÍÛ°ì, ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¾éĹ²½Àß·×Wallace Tree·¿¾è»»´ï¤Î»îºî1," "Ʊ2," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, ¶¦¤Ë p.210, 2005.
• ÆñÇÈ °ìµ±, °ËÆ£ ½¨ÃË, "¾éĹ¥Ñ¥¹¤òÍ­¤¹¤ë¥Þ¥ë¥Á¥³¥ó¥Æ¥­¥¹¥ÈFPGA," ÅìµþÂç³ØÂ絬ÌϽ¸ÀÑ¥·¥¹¥Æ¥àÀ߷׶µ°é¥»¥ó¥¿¡¼Ç¯Êó, p.210, 2004.

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